The present invention relates to digital integrated circuits for implementing logic functions and, more particularly, to a binary multiplier circuit comprising subcircuits all of which are implemented using exclusively transmission gate multiplexer (TGM) circuits.
Every designer and manufacturer of integrated circuits currently faces two formidable obstacles to performance improvements. First, further increases in circuit density require design and implementation of sub-micron feature size devices. This effort requires vast investments of resources in new equipment and techniques. Second, even assuming success in building sub-micron devices, operation of circuits with transistor gate lengths substantially smaller than one micron is limited by breakdown voltages less than the five volt supply voltage level now standard for virtually all logic devices throughout the industry. Lower supply voltages compromise noise immunity and are incompatible with existing components and systems. Substantial investment in research, development and implementation of new processes and materials is being made in an attempt to overcome these limitations.
Such changes are likely to come about relatively slowly. In the interim, improved performance must be achieved by improved designs using existing technologies.
Several families of integrated circuits are known for implementing a wide variety of logic functions. Logic families include the various forms of TTL, ECL, MOS, CMOS and the like. These various logic families offer the logic circuit designer the ability to trade off speed, size, power consumption, noise immunity and other considerations by selecting a logic family accordingly. Tradeoffs must be made as no single logic family to date is an outstanding performer in all of these categories.
Improvements in performance of some kinds of logic circuits have been achieved through the use of pass transistors or transmission gate structures. A transmission gate multiplexer offers speed and area characteristics superior to known logic circuit designs.
However, design of logic circuits using such technologies, particularly design of higher order logic functions (for example, functions of greater than three variables) remains a challenge.
U.S. Pat. No. 4,710,649 (Lewis) discloses transmission gate logic circuits for implementing fundamental boolean combinations such as AND and OR functions. The '649 patent shows simplified or reduced versions of two and three input AND and OR gates for reducing transistor count, and suggests cascading additional stages to form a circuitry for implementing higher order functions. When extended to higher order boolean functions however, the resultant circuits are not optimal. (See the discussion of FIG. 3, below.)
U.S. Pat. No. 4,566,064 (Whitaker) presents a design methodology for constructing circuits using pass transistors to implement logic functions. The method disclosed in the '064 patent, however, has several drawbacks. A substantial propagation delay results from connecting more than two transmission gate outputs in parallel. This results in larger output parasitic capacitants, a major contributor to delay in CMOS designs. For a large number of inputs, the number of required circuit elements, such as transmission gates, increases geometrically with the number of input variables. Finally, circuits designed as described in the '064 patent are difficult to simulate on existing gate-level simulation programs because two or more transmission gate output terminals can be ON in parallel, thus requiring the simulator software to resolve this apparent driver conflict by applying varied signal strengths.
A basic primer on CMOS transmission gates and their use is E. Hnatek, USER'S GUIDEBOOK TO DIGITAL CMOS INTEGRATED CIRCUITS (McGraw-Hill 1981) pp. 34-41. A combinational multiplier circuit that includes the use of transmission gates in an adder cell is shown in R. R. Shively, et al. "Cascading Transmission Gates to Enhance Multiplier Performance" IEEE Transactions on Computers, Vol. c-33, No. 7, July, 1984. Pass transistor logic is used in "A 3.8 ns 16.times.16 Multiplier Using Complementary Pass Transistor Logic," by K. Yano, et al, IEEE 1989 Custom Integrated Circuits Conference. The problem of digital signal propagation delay through a string of pass transistors is recognized, and a solution suggested, in U.S. Pat. No. 4,536,855 (Morton). An MOS binary multiplication cell circuit with reduced transistor count is shown in U.S. Pat. No. 4,363,107 (Ohhashi et al.).
Accordingly, the need remains for better designs of TGM logic circuits to gain improvements in speed and performance over the state of the art.